1. Field of the Disclosure
The present disclosure generally relates to a structure and method for the creation of on-chip thermal heat sinks for active, passive or discrete integrated circuit applications specifically for the application of embedded die in printed circuit boards.
2. State of the Art
Semiconductor wafers consist of multiple arrays of devices often referred to as chips or die which are later separated into individual discrete devices, a process known as “singulation”. After singulation, these chips are further integrated into a chip package and then mounted onto a printed circuit board during final board assembly for the particular end product. A relatively new and upcoming technique is to combine the chip packaging and the printed circuit board assembly with a process of embedding the chip into a printed circuit board.
Assembly of large PWB substrate sizes with multiple embedded die PWB's in a step and repeat format is desirable to improve economy of scale. It is also desirable to increase component density in order to reduce total package footprint.
In many passive, active or discrete semiconductor circuit applications, it is desirable to provide adequate heat sinking of the chip circuitry to ensure optimal chip, and total system performance. Heat sinking allows the chip to perform its function more efficiently at a given power load and allows higher reliability of the chip and the adjacent chip and other devices, since heat generally degrades the performance of most semiconductors.
Typically on-chip heat sinking is achieved by electroplating thick metals with good thermal conductivity, such as copper, or a copper alloy, in the desired hotspot region on the chip. This aids heat dissipation into the surrounding package and ambient environment. This process is typically performed on a semiconductor wafer either at the wafer foundry or at the final wafer level packaging supplier. However, a wafer level process offers significant cost advantages as multiple heat sinks can be created simultaneously in the normal wafer level manufacturing process steps.
Heat sinks can also be placed discretely with post wafer processing on individual singulated devices, chips or die. Typically, on-chip heat sinks are created by electroplated copper processes. However, increasing the plating area or the plating thickness increases process cost. Thus it is desirable to identify a low cost, high volume alternative process for large surface area structures.
Thermal dissipation management by heat-sinking is particularly problematic in the newer embedded chip or die package applications where the chip is encapsulated by the PWB (printed wiring board). Polymeric materials used in the PWB core and subsequent build up layers typically have low thermal conductivity compared to plated metals or applied metal foils. In the embedded chip application, the chip is separated by one or more buildup layers from the external surface of the printed circuit board where air or metal heat sinks can assist in thermal dissipation management. Therefore an embedded chip is susceptible to higher operating temperatures for a given power load.
In the encapsulated embedded chip application, it can also be necessary to provide adequate thermal dissipation to both the front side and back side of the embedded component to assist in removing heat to the surface or sides of the PWB. Thus there is a need for a cost effective wafer level process particularly in the embedded chip or die manufacturing process that incorporates increased heat sink capabilities.